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1 features ? programmable 4,194,304 x 1 and 8,388,608 x 1-bit serial memories designed to store configuration programs for field programmable gate arrays (fpgas) 3.3v output capability 5v tolerant i/o pins program support using the atmel atdh2200e system or industry third party programmers in-system programmable (isp) via 2-wire bus simple interface to sram fpgas compatible with atmel at40k and at94k devices, altera flex ? , apex ? devices, lucent orca ? fpgas, xilinx xc3000 ? , xc4000 ? , xc5200 ? , spartan ? , virtex ? fpgas, motorola mpa1000 fpgas cascadable read-back to support additional configurations or higher-density arrays low-power cmos flash process available in 6 mm x 6 mm x 1 mm 8-lead lap (pin-compatible with 8-lead soic/voic packages), 20-lead plcc, 44-lead plcc and 44-lead tqfp packages emulation of atmel?s at24cxxx serial eeproms low-power standby mode single device capable of holding 4 bit stream files allowing simple system reconfiguration fast serial download speeds up to 33 mhz endurance: 10,000 write cycles typical description the at17f series of in-system programmable configuration proms (configurators) provide an easy-to-use, cost-effective configuration memory for field programmable gate arrays. the at17f series device is packaged in the 8-lead lap, 20-lead plcc, 44-lead plcc and 44-lead tqfp, see table 1. the at17f series configurator uses a simple serial-access procedure to configure one or more fpga devices. the at17f series configurators can be programmed with industry-standard program- mers, atmel?s atdh2200e programming kit or atmel?s atdh2225 isp cable. table 1 . at17f series packages package AT17F040 at17f080 8-lead lap yes yes 20-lead plcc yes yes 44-lead plcc ? yes 44-lead tqfp ? yes fpga configuration flash memory AT17F040 at17f080 rev. 3039f?cnfg?2/04
2 AT17F040/080 3039f?cnfg?2/04 pin configuration 8-lead lap 20-lead plcc 20-lead plcc (virtex ? pinout) (1)(2) notes: 1. 20-lead plcc (virtex ? pinout) is only available in the AT17F040. 2. virtex pinout is compatible with the xc17v and xc18v series prom. 8 7 6 5 1 2 3 4 data clk reset/oe ce vcc ser_en ceo (a2) gnd 4 5 6 7 8 18 17 16 15 14 clk nc reset/oe pagesel1 ce nc ser_en page_en ready ceo (a2) 3 2 1 20 19 9 10 11 12 13 nc gnd pagesel0 nc nc nc data nc vcc nc 4 5 6 7 8 18 17 16 15 14 nc nc nc nc reset/oe ser_en nc nc ready nc 3 2 1 20 19 9 10 11 12 13 nc ce gnd nc ceo (a2) clk nc data vcc nc
3 AT17F040/080 3039f?cnfg?2/04 44 plcc 44 tqfp 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 nc reset/oe pagesel0 ce nc nc gnd pagesel1 nc ceo/a2 nc nc clk nc nc data page_en vcc nc nc ser_en nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ready 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 nc reset/oe pagesel0 ce nc nc gnd pagesel1 nc ceo(a2) nc nc clk nc nc data page_en vcc nc nc ser_en nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc ready
4 AT17F040/080 3039f?cnfg?2/04 block diagram device description the control signals for the configuration memory device (ce , reset /oe and clk) interface directly with the fpga device control signals. all fpga devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. the reset /oe and ce pins control the tri-state buffer on the data output pin and enable the address counter. when reset /oe is driven low, the configuration device resets its address counter and tri-states its data pin. the ce pin also controls the out- put of the at17f series configurator. if ce is held high after the reset /oe reset pulse, the counter is disabled and the data output pin is tri-stated. when oe is subse- quently driven high, the counter and the data output pin are enabled. when reset /oe is driven low again, the address counter is reset and the data output pin is tri-stated, regardless of the state of ce . when the configurator has driven out all of its data and ceo is driven low, the device tri-states the data pin to avoid contention with other configurators. upon power-up, the address counter is automatically reset. config. page select power-on reset flash memory clock/oscillator logic 2-wire serial programming serial download logic control logic clk ceo(a2) data ce reset/oe ser_en ce/we/oe data address ready page_en pagesel0 pagesel1 reset
5 AT17F040/080 3039f?cnfg?2/04 data (1) three-state data output for configuration. open-collector bi-directional pin for programming. clk (1) clock input. used to increment the internal address and bit counter for reading and programming. pag e _ e n (2) input used to enable page download mode. when page_en is high the configuration download address space is partitioned into 4 equal pages. this gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. this input works in conjunction with the pagesel inputs. page_en must be remain low if paging is not desired. when ser_en is low (isp mode) this pin has no effect. notes: 1. this pin has an internal 20 k ? pull-up resistor. 2. this pin has an internal 30 k ? pull-down resistor. pin description name i/o AT17F040 at17f080 8 lap 20 plcc 20 plcc (virtex) 8 lap 20 plcc 44 plcc 44 tqfp data i/o12112240 clk i24324543 page_eni?16? ?16139 pagesel0 i ? 11 ? ? 11 20 14 pagesel1 i ? 7 ? ? 7 25 19 reset /oei368361913 ce i4 8104 82115 gnd ? 5 10 11 5 10 24 18 ceo o 6 14 13 6 14 27 21 a2 i ready o ? 15 15 ? 15 29 23 ser_en i7 1718 7 174135 v cc ?8 2020 8 204438
6 AT17F040/080 3039f?cnfg?2/04 pagesel[1:0] (2) page select inputs. used to determine which of the 4 memory pages are targeted during a serial configuration download. the address space for each of the pages is shown in table 2. when ser_en is low (isp mode) these pins have no effect. reset /oe (1) output enable (active high) and reset (active low) when ser_en is high. a low level on reset /oe resets both the address and bit counters. a high level (with ce low) enables the data output driver. ce (1) chip enable input (active low). a low level (with oe high) allows clk to increment the address counter and enables the data output driver. a high level on ce disables both the address and bit counters and forces the device into a low-power standby mode. note that this pin will not enable/disable the device in the 2-wire serial programming mode (ser_en low). gnd ground pin. a 0.2 f decoupling capacitor between v cc and gnd is recommended. ceo chip enable output (when ser_en is high). this output goes low when the internal address counter has reached its maximum value. if the page_en input is set high, the maximum value is the highest address in the selected partition. the pagesel[1:0] inputs are used to make the 4 partition selections. if the page_en input is set low, the device is not partitioned and the address maximum value is the highest address in the device, see table 2 on page 6. in a daisy chain of at17f series devices, the ceo pin of one device must be connected to the ce input of the next device in the chain. it will stay low as long as ce is low and oe is high. it will then follow ce until oe goes low; thereafter, ceo will stay high until the entire eeprom is r ead again. a2 (1) device selection input, (when ser_en low). the input is used to enable (or chip select) the device during programming (i.e., when ser_en is low). refer to the at17f programming specification available on the atmel web site for additional details. ready open collector reset state indicator. driven low during power-up reset, released when power-up is complete. (recommended 4.7 k ? pull-up on this pin if used). ser_en (1) the serial enable input must remain high during fpga configuration operations. bring- ing ser_en low enables the 2-wire serial programming mode. for non-isp applications, ser_en should be tied to v cc . v cc +3.3v (10%). notes: 1. this pin has an internal 20 k ? pull-up resistor. 2. this pin has an internal 30 k ? pull-down resistor. table 2. address space paging decodes AT17F040 (4 mbits) at17f080 (8 mbits) pagesel = 00, page_en = 1 00000 ? 0ffffh 00000 ? 1ffffh pagesel = 01, page_en = 1 10000 ? 1ffffh 20000 ? 3ffffh pagesel = 10, page_en = 1 20000 ? 2ffffh 40000 ? 5ffffh pagesel = 11, page_en = 1 30000 ? 3ffffh 60000 ? 7ffffh pagesel = xx, page_en = 0 00000 ? 3ffffh 00000 ? 7ffffh
7 AT17F040/080 3039f?cnfg?2/04 fpga master serial mode summary the i/o and logic functions of any sram-based fpga are established by a configura- tion program. the program is loaded either automatically upon power-up, or on command, depending on the state of the fpga mode pins. in master mode, the fpga automatically loads the configuration program from an external memory. the at17f serial configuration prom has been designed for compatibility with the master serial mode. this document discusses the atmel at40k, at40kal and at94kal applications as well as xilinx applications. control of configuration most connections between the fpga device and the at17f serial configurator prom are simple and self-explanatory. the data output of the at17f series configurator drives din of the fpga devices. the master fpga cclk output drives the clk input of the at17f series configurator. the ceo output of any at17f series configurator drives the ce input of the next configurator in a cascade chain of configurator devices. ser_en must be connected to v cc (except during isp). the ready pin is available as an open-collector indicator of the device?s reset status; it is driven low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. page_en must be held low if download paging is not desired. the pagesel[1:0] inputs must be tied off high or low. if paging is desired, page_en must be high and the pagesel pins must be set to high or low such that the desired page is selected, see table 2 on page 6. cascading serial configuration devices for multiple fpgas configured as a daisy-chain, or for fpgas requiring larger configu- ration memories, cascaded configurators provide additional memory. after the last bit from the first configurator is read, the clock signal to the configurator asserts its ceo output low and disables its data line driver. the second configurator recognizes the low level on its ce input and enables its data output. after configuration is complete, the address counters of all cascaded configurators are reset if the reset /oe on each configurator is driven to its active (low) level. if the address counters are not to be reset upon completion, then the r eset /oe input can be tied to its inactive (high) level. programming mode the programming mode is entered by bringing ser_en low. in this mode the chip can be programmed by the 2-wire serial bus. the programming is done at v cc supply only. programming super voltages are generated inside the chip. the at17f parts are read/write at 3.3v nominal. refer to the at17f programming specification available on the atmel web site (www.atmel.com) for mo re programming details . at17f devices are supported by the atmel atdh2200 programming system along with many third party programmers. standby mode the at17f series configurators enter a low-power standby mode whenever ser_en is high and ce is asserted high. in this mode, the at17f configurator consumes less than 1 ma of current at 3.3v. the output remains in a high-impedance state regardless of the state of the oe input.
8 AT17F040/080 3039f?cnfg?2/04 absolute maximum ratings* operating temperature .................................... -40 c to +85 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under oper- ating conditions is not implied. exposure to abso- lute maximum rating conditions for extended periods of time may affect device reliability. storage temperature ..................................... -65 c to +150 c voltage on any pin with respect to ground ..............................-0.1v to v cc +0.5v supply voltage (v cc ) .........................................-0.5v to +4.0v maximum soldering temp. (10 sec. @ 1/16 in.).............260 c esd (r zap = 1.5k, c zap = 100 pf)................................. 2000v operating conditions symbol description at17f series configurator units min max v cc commercial supply voltage relative to gnd -0 c to +70 c 2.97 3.63 v industrial supply voltage relative to gnd -40 c to +85 c 2.97 3.63 v dc characteristics symbol description AT17F040 at17f080 units minmaxminmax v ih high-level input voltage 2.0 v cc 2.0 v cc v v il low-level input voltage 0 0.8 0 0.8 v v oh high-level output voltage (i oh = -2.5 ma) commercial 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 v v oh high-level output voltage (i oh = -2 ma) industrial 2.4 2.4 v v ol low-level output voltage (i ol = +3 ma) 0.4 0.4 v i cca supply current, active mode 20 20 ma i l input or output leakage current (v in = v cc or gnd) -10 10 -10 10 a i ccs supply current, standby mode commercial 1 1 ma industrial 1 1 ma
9 AT17F040/080 3039f?cnfg?2/04 ac characteristics ac characteristics when cascading ce reset/oe clk data t sce t lc t hc t cac t oe t ce t oh t hoe t sce t hce t df t oh ce reset/oe clk data ceo t cdf t ock t oce t oce t ooe last bit first bit
10 AT17F040/080 3039f?cnfg?2/04 notes: 1. preliminary specifications for military operating range only. 2. ac test lead = 50 pf. 3. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. 4. see the at17f programming specfication for procedural information. ac characteristics symbol description AT17F040 at17f080 units min max min max t oe (2) oe to data delay commercial 50 50 ns industrial (1) 55 55 ns t ce (2) ce to data delay commercial 60 55 ns industrial (1) 60 60 ns t cac (2) clk to data delay commercial 30 3 30 ns industrial (1) 30 30 ns t oh data hold from ce , oe, or clk commercial 0 0 ns industrial (1) 00ns t df (3) ce or oe to data float delay commercial 15 15 ns industrial (1) 15 15 ns t lc clk low time commercial 15 15 ns industrial (1) 15 15 ns t hc clk high time commercial 15 15 ns industrial (1) 15 15 ns t sce ce setup time to clk (to guarantee proper counting) commercial 35 20 ns industrial (1) 40 25 ns t hce ce hold time from clk (to guarantee proper counting) commercial 0 0 ns industrial (1) 00ns t hoe reset/oe low time (guarantees counter is reset) commercial 20 20 ns industrial (1) 20 20 ns f max maximum input clock frequency seren = 0 commercial 10 10 mhz industrial (1) 10 10 mhz f max maximum input clock frequency seren = 1 commercial 33 33 mhz industrial (1) 33 33 mhz t wr write cycle time (4) commercial 30 30 s industrial (1) 30 30 s t ec erase cycle time (4) commercial 30 10 s industrial (1) 30 10 s
11 AT17F040/080 3039f?cnfg?2/04 notes: 1. ac test lead = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured 200 mv from steady-state active levels. ac characteristics when cascading symbol description AT17F040 at17f080 units minmaxminmax t cdf (3) clk to data float delay commercial 60 50 ns industrial 60 50 ns t ock (2) clk to ceo delay commercial 55 50 ns industrial 60 55 ns t oce (2) ce to ceo delay commercial 55 35 ns industrial 60 40 ns t ooe (2) reset /oe to ceo delay commercial 40 35 ns industrial 45 35 ns f max maximum input clock frequency commercial 33 33 mhz industrial 33 33 mhz
12 AT17F040/080 3039f?cnfg?2/04 note: 1. airflow = 0 ft/min. thermal resistance coefficients package type AT17F040 at17f080 8cn4 leadless array package (lap) jc [ c/w] ? ja [ c/w] (1) ? 20j plastic leaded chip carrier (plcc) jc [ c/w] ? ja [ c/w] (1) ? 44a thin plastic quad flat package (tqfp) jc [ c/w] ? 17 ja [ c/w] (1) ?62 44j plastic leaded chip carrier (plcc) jc [ c/w] ? 15 ja [ c/w] (1) ?50
13 AT17F040/080 3039f?cnfg?2/04 ordering information memory size ordering code package operation range 4-mbit AT17F040-30cc AT17F040-30jc AT17F040-30vjc 8cn4 - 8 lap 20j - 20 plcc 20j - 20 plcc commercial (0 c to 70 c) AT17F040-30ci AT17F040-30ji AT17F040-30vji 8cn4 - 8 lap 20j - 20 plcc 20j - 20 plcc industrial (-40 c to 85 c) 8-mbit at17f080-30cc at17f080-30jc at17f080-30tqc at17f080-30bjc 8cn4 - 8 lap 20j - 20 plcc 44a - 44 tqfp 44j - 44 plcc commercial (0 c to 70 c) at17f080-30ci at17f080-30ji at17f080-30tqi at17f080-30bji 8cn4 - 8 lap 20j - 20 plcc 44a - 44 tqfp 44j - 44 plcc industrial (-40 c to 85 c) package type 8cn4 8-lead, 6 mm x 6 mm x 1 mm, leadless array package (lap) ? pin-compatible with 8-lead soic/void packages 20j 20-lead, plastic j-leaded chip carrier (plcc) 44a 44-lead, thin (1.0 mm) plastic quad flat package carrier (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc)
14 AT17F040/080 3039f?cnfg?2/04 packaging information 8cn4 ? lap 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8cn4 , 8-lead (6 x 6 x 1.04 mm body), lead pitch 1.27 mm, leadless array package (lap) a 8cn4 11/14/01 pin1 corner marked pin1 indentifier 0.10 mm typ 4 3 2 1 5 6 7 8 top view l b e l1 e1 side view a1 a bottom view e d common dimensions (unit of measure = mm) symbol min nom max note a 0.94 1.04 1.14 a1 0.30 0.34 0.38 b 0.45 0.50 0.55 1 d 5.89 5.99 6.09 e 4.89 5.99 6.09 e 1.27 bsc e1 1.10 ref l 0.95 1.00 1.05 1 l1 1.25 1.30 1.35 1 note: 1. metal pad dimensions.
15 AT17F040/080 3039f?cnfg?2/04 20j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
16 AT17F040/080 3039f?cnfg?2/04 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
17 AT17F040/080 3039f?cnfg?2/04 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
printed on recycled paper. 3039f?cnfg?2/04 xm disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof, are the registered trademarks of atmel corporation or its subsidiaries. flex ? is the trademarks of altera corporation. orca ? is the trademark of lucent technologies, inc. spartan ? and virtex ? are the registered trademarks, and xc3000 ? , xc4000 ? and xc5200 ? are the trademarks of xilinx, inc. apex ? is the trademark of mips technolo- gies. other terms and product names may be the trademarks of others.

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